Accurate modeling of semiconductor devices is needed to provide reliable circuit simulation results that can predict the behavior of a semiconductor circuit. Often, circuit simulations are used during a design phase of a circuit to predict circuit characteristics such as the drive current of an individual circuit component, the signal delay between multiple circuit components, or the overall performance of a circuit in terms of the operating speed of a chip and interaction with other chips.
Stress impacts the performance of semiconductor devices by altering the band structure of the semiconductor material, and consequently, the mobility of carriers. This effect is prominent in metal-oxide-semiconductor field effect transistor (MOSFET) devices since the transconductance of a MOSFET is impacted by the mobility of minority carriers in the body. For example, the hole mobility of a p-type MOSFET formed on a silicon substrate increases under a uniaxial compressive stress in the direction of the channel, i.e., along a line connecting the source and the drain. The electron mobility of an n-type MOSFET formed on a silicon substrate increases under a tensile stress in the direction of the channel. The change in the mobility of minority carriers depends on the type and direction of stress as well as the semiconductor substrate material.
Various methods of imparting stress on semiconductor devices have been known in the art, including strained layers formed in the semiconductor substrate, stress liners formed over a semiconductor device, and embedding a stress inducing material such as silicon germanium alloy within the semiconductor structure, e.g., within the source and drain regions of a MOSFET. Stress engineering has produced substantial improvement in the performance of semiconductor devices in general. However, the degree of improvement in the performance depends on the level of stress applied to the semiconductor device, e.g., on the level of stress applied to the channel of a MOSFET.
As a physical quantity, stress is defined at every point in a semiconductor device as a three-dimensional tensor, thus forming a tensor field within a semiconductor structure. Since the stress is generated by physical structures, variations in the arrangement in the physical structures around the semiconductor device results in variations in the stress. Thus, accurate modeling of semiconductor devices requires modeling of the effects of stress on semiconductor devices. Methods of modeling stress in semiconductor devices for device modeling and circuit simulation purposes are described in commonly-assigned, copending U.S. patent application Ser. No. 11/193,711, filed on Jul. 29, 2005, the contents of which are incorporated herein by reference.
Since stress is affected by many physical structures around a semiconductor device, stress modeling takes into account the variation of stress due to the physical structures around the semiconductor device structure in concern. Of utmost importance is the type and location of stress generating structures, such as stress-generating substrate layers, stress liners, and embedded stress-generating materials. The type and location of other physical structures that affect the transmission of stress also affects the stress applied to the semiconductor device.
Referring to FIG. 1, an exemplary semiconductor layout is provided in which a channel of a MOSFET is located in the area of the overlap of a gate 2 and an active area 6. The gate 2 is called a “victim gate” since the stress in concern is applied to the channel underneath the gate 2. Representations of physical structures that affect the stress on the channel of a physical MOSFET corresponding to the victim gate 2 include the victim gate 2 itself, another gate 3, contact bars 4 that represent metallic contact structures located directly on the active area 6, for example, source and drain regions of MOSFETs, the active area 6, shallow trench isolation (8, 8′), and the boundary 9 between one type of stress liner and another type of stress liner. In FIG. 1, the boundary 9 divides the shallow trench isolation into a first portion 8 with one type of stress liner and another portion 8′ with another type of liner. While FIG. 1 illustrates representations of some exemplary structures, the stress applied to the channel underneath the victim gate, may be in general affected by many other types of physical structures that are represented in a layout by other objects, or instances that belong to other shape classes.
During modeling of stress, the physical structures are categorized into predefined stress-affecting shape classes with associated numbers that characterize the physical structure. During the design phase of a circuit, each of the physical structures is represented by an object, or an instance in a shape class. Examples of shape classes include the class of active areas defined in a design level called RX (recessed oxide), the class of gate conductors defined in a design level called PC (polysilicon conductor), the class of contact bars defined in a design level called MC (metal contact), the class of boundaries between one type of stress liner and another type of stress liner, which is defined in a level called BP (block p-type implantation), etc. Stud contacts are also contemplated as a shape class. Typically, many types of shape classes are defined in addition to those listed above to reflect the different stress characteristics of the corresponding physical structures. Instances of each of the shape classes typically include geometrical shapes in the design layout that defines a physical semiconductor structure. For example, an instance of the shape class of gate conductors is the gate conductor 3 in FIG. 1.
To calculate the stress on the channel beneath the victim gate 2, shape dimensions characterizing the geometrical aspects of an instance in a shape class are used in the calculation of stress contribution. This calculation is repeated for each instance in each shape class. Some exemplary shape dimensions shown in FIG. 1 include the width W of the active area 6 for an instance of active areas, the distance PC-PCW from the western edge (when the layout is viewed in the same manner as viewing a map) of the victim gate 2 to the wall of the first gate 3 located to the west, the dimensions (MCEW, MCEL, MCWW, MCWL, MC2WW, MC2WL) of the contact bars 4 around the victim gate 2, the distances (PC-MCE, PC-MCW, PC-MC2W) from the victim gate 2 to the contact bars 4, the distances (PC-RXE, PC-RXW) between edges of the victim gate 2 to the edges of the active area 6, the distances (PC-BPN, PC-BPS, PC-BPE, PC-BPW) to the closest northern, southern, eastern, and western edges of the boundary 9 between different types of stress liners, etc. Use of FIG. 1 herein is only for exemplary purposes. Typically, multiple instances, each of which belongs to any one of the multiple shape classes and characterized by different shape dimensions, contribute to the stress on the channel of a MOSFET.
As described above, the stress on the channel of a MOSFET is a three-dimensional tensor field defined within the volume of the MOSFET. In standard wafers with (001) surface direction and a (110) channel orientation, the primary components of stress that affect the devices are longitudinal and transverse stresses. Here the longitudinal stress is defined as the stress in the direction of current flow and the transverse stress is the stress normal to direction of current flow in the device width direction. The primary focus is on longitudinal and transverse stress components because the other stress components are expected to be less sensitive to layout changes. The stress effect of the stress tensor field within the MOSFET is three-dimensional and non-uniform, but it may be approximated analytically by a channel stress vector. These analytical solutions represent the average stress in the channel in the longitudinal and transverse directions.
Based on the relevant and critical sensitivities, the full three-dimensional stress tensor field within the MOSFET can be approximated and represented as a two component vector. In this two-dimensional vector approximation, channel stress is decomposed into average longitudinal and transverse stress components. These components are defined to reflect the average effect of stress on carriers as they traverse the channel. The longitudinal stress terms can be further decomposed into a self-stress term σself and terms that reflect the influence of adjacent structures on the channel stress, such as a contact structure stress term σCA, a gate conductor structure stress term σPC, a shallow trench isolation stress longitudinal component term σRXL, a liner boundary stress longitudinal component term σDSLL, and an embedded material generated stress term σeSiGe. The transverse stress terms can be further decomposed into a body contact structure stress term σBC (in the case of a semiconductor-on-insulator substrate), a shallow trench isolation stress transverse component term σRXT, a liner boundary stress transverse component term σDSLT.σL=σself+σCA+σPC+σRXL+σDSLL+σeSiGe  (B.1)σT=σBC+σRXT+σDSLT  (B.2)
The individual terms carry their own sign, i.e., may be positive or negative. The total longitudinal stress σL includes the contribution from the left and right sides of the gate being analyzed in a design layout, left and right being oriented in the direction of the current flow, i.e., in the direction connecting the source and the drain in a physical MOSFET. The total transverse stress σT includes the liner boundary stress transverse component term from the top and bottom of the gate being analyzed in the design layout, top and bottom being oriented in the plane of the semiconductor substrate surface and perpendicular to the direction of the current flow, as well as any shallow trench isolation transverse stress.σL=σleftL+σrightL  (B.3)σT=σtopT+σbottomT  (B.4)
The channel stress thus computed may be utilized to improve the accuracy of a compact model in predicting compact model parameters. For example, the compact model parameters may be the carrier mobility in the channel of a MOSFET.
Referring to FIG. 2, a prior art method of computing model parameters in a compact model, as described in the above-mentioned U.S. Patent Application, is shown. The compact model comprises a base model and a stress model. Model parameters, such as carrier mobility in the channel of a MOSFET, are calculated by computing stress using the stress model and using it in the formula for the model parameter.
The base model is calibrated from a length scaling macro, i.e., a suite of transistors with varying gate length L (the distance between the source and the drain) and varying gate width W, while instances of other shape classes remain constant in the layout. This is the conventional way compact models are calibrated in the absence of stress effects. The stress model is calibrated with a layout-dependency macro, a suite of transistors with the same gate length L, while instances of other shape classes are varied.
Due to the large amount of time and resources required during the compact model build, the base model and the stress model are assembled independently. The assembled compact model must be self-consistent for channel length scaling, for example, in predicting the model parameters of the length scaling macros. However, channel length scaling may not be self-consistent because the base model inadvertently includes a component of channel length scaling introduced by the length dependent engineered stress, such as self stress. Since the stress model is theory-based and created independently of the base model, the prior art method is prone to overcompensating or undercompensating the stress effects for MOSFET devices with a different gate length than the one on which the stress model is built.
Concerning the accuracy of the prior art stress model, the carrier mobility in the channel is approximated by the composite mobility response to longitudinal and transverse stress, which is given by equation (B.5).μ(σ)=μ(σL,σT)=μ0×(c2LσLσL+c1LσL+c0L+c2TσTσT+c1TσT+c0T)  (B.5)
The quantities σL, σT, and μ(σL, σT) are calculated by fitting measured data from physical semiconductor devices constructed using layout-dependency macros, i.e., a layout of multiple semiconductor devices designed to calculate σL, σT, and μ(σL,σT) from measured values of device parameters in each of the semiconductor devices. The term μ0 is calculated during the base model calibration. Since the fitting for σL and σT is performed with a data set from the layout-dependency macro, correction of self-stress for non-nominal device length is not provided according to the prior art. In other words, the calculated self-stress values are calibrated only for the device length that is used in the layout-dependency macro, which is typically the nominal device length.
Therefore, there exists a need for a methodology for providing an accurate stress model that is self-consistent with the data set generated from dimension-scaling macros in a compact model.
Also, there exists a need for a methodology for calculating model parameters with accurate constant, linear, and quadratic coefficients for a layout variable in a dimension-scaling macro to better predict the impact of stress on the model parameter.
Further, there exists a need for a system for modeling semiconductor devices employing an accurate stress model and accurate model parameters that are self-consistent with measurement data from dimension-scaling macros and has accurate constant, linear, and quadratic term coefficients for a layout variable in a dimension-scaling macro.
In addition, there exists a need for a system for simulating semiconductor circuit and/or optimizing semiconductor circuit that employs the accurate stress model and accurate model parameters that are self-consistent with measurement data from dimension-scaling macros and have accurate constant, linear, and quadratic term coefficients for a layout variable in a dimension-scaling macro.